View A3-44PA-2SV_44024.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 512Mb C-die with 72-bit ECC
66 TSOP-II and 60 ball FBGA with Pb-Free (RoHS compliant)
.com
DataShee
Revision 0.1 October. 2004
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Revision History
Revision 0.0 (September, 2004) - First release Revision 0.1 (October, 2004) - Changed IDD current.
Preliminary DDR SDRAM
t4U.com
.com
DataShee
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
184Pin Registered DIMM based on 512Mb C-die (x4, x8)
Ordering Information
Part Number M312L6523CUS-CB3/A2/B0 M312L2923CUS-CB3/A2/B0 M312L2920CUS-CB3/A2/B0 M312L5628CU0-CA2/B0 M312L6523CZ0-CCC/B3/A2/B0 M312L2923CZ0-CCC/B3/A2/B0 M312L2920CZ0-CCC/B3/A2/B0 M312L5720CZ0-CCC/B3/A2/B0 Density 512MB 1GB 1GB 2GB 512MB 1GB 1GB 2GB Organization 64M x 72 128M x 72 128M x 72 256M x 72 64Mx72 128M x 72 128M x 72 256M x 72
Preliminary DDR SDRAM
Component Composition 64Mx8( K4H510838C) * 9EA 64Mx8( K4H510838C) * 18EA 128Mx4( K4H510438C) * 18EA st.256Mx4( K4H1G0638C) * 18EA 64Mx8( K4H510838C) * 9EA 64Mx8( K4H510838C) * 18EA 128Mx4( K4H510438C) * 18EA 128Mx4( K4H510438C) * 36EA
Height 1,200mil 1,200mil 1,200mil 1,200mil 1,125mil 1,125mil 1,125mil 1,200mil
Operating Frequencies
CC(DDR400@CL=3) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP 166MHz 200MHz 3-3-3 B3(DDR333@CL=2.5) 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
t4U.com
.com
DataShee
Feature
* VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 * VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400 * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * SSTL_2 Interface * 66pin TSOP II and 60 ball FBGA Pb-Free package * RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Pin Configuration (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Front VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC /RESET VSS DQ8 DQ9 DQS1 VDDQ *CK1 */CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 Pin 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 Front A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD DQS8 A0 CB2 VSS CB3 BA1 Pin 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Front Pin Back Pin 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 Back VSS A6 DQ28 DQ29 VDDQ DM3/DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 /CK0 VSS DM8/DQS17 A10 CB6 VDDQ CB7
Preliminary DDR SDRAM
Pin 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
Back /RAS DQ45 VDDQ /CS0 /CS1 DM5/DQS14 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6/DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DM7/DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD
KEY
DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40
t4U.com
VSS 93 VDDQ DQ4 94 /WE DQ5 95 DQ41 VDDQ 96 /CAS DM0/DQS9 97 VSS DQ6 98 DQS5 DQ7 99 DQ42 VSS 100 DQ43 NC 101 VDD NC 102 */CS2 NC 103 DQ48 VDDQ 104 DQ49 DQ12 105 VSS DQ13 106 *CK2 DM1/DQS10 107 */CK2 VDD 108 VDDQ DQ14 109 DQS6 DQ15 110 DQ50 CKE1 111 DQ51 VDDQ 112 VSS *BA2 113 VDDID DQ20 114 DQ56 A12 115 DQ57 VSS 116 VDD DQ21 117 DQS7 A11 118 DQ58 DM2/DQS11 119 DQ59 VDD 120 VSS .com DQ22 121 NC A8 122 SDA DQ23 123 SCL
KEY
VSS DQ36 DQ37 VDD DM4/DQS13 DQ38 DQ39 VSS DQ44
DataShee
Note : 1. * : These pins are not used in this module. 2. Pins 111, 158 are NC for 1row module & used for 2row module. 3. Pins 97, 107, 119, 129, 140, 149, 159, 169, 177 : DM (x8 base module) or DQS (x4 base module).
Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 DQS0 ~ DQS17 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7 Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name DM0 ~ DM8 VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 NC Data - in mask Power supply (2.5V for DDR266/333, 2.6V for DDR400) Power Supply for DQS (2.5V for DDR266/333, 2.6V for DDR400) Ground Power supply for reference Serial EEPROM Power/Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM No connection Function
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
512MB, 64M x 72 ECC Module (M312L6523CUS) (Populated as 1 bank of x8 DDR SDRAM Module) Functional Block Diagram
RCS0 DQS0 DM0
DM/ CS DQS
DQS4 DM4
DM/ CS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1
I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1
D0
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D4
DM/
CS
DQS
DM/
CS
DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6
I/O 7 I/O 4 I/O 2 I/O 0 I/O 6 I/O 5 I/O 3 I/O 1
D5
DM/
CS
DQS
DM/
CS
DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3
I/O 6 I/O 5 I/O 3 I/O 1 I/O 7 I/O 4 I/O 2 I/O 0
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D6
t4U.com
DM/
CS
DQS
.com DM/ CS DQS
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 6 I/O 4 I/O 2 I/O 0 I/O 7 I/O 5 I/O 3 I/O 1
DataShee
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8
I/O 0 I/O 2 I/O 5 I/O 6 I/O 1 I/O 3 I/O 4 I/O 7
D3
D7
DM/
CS
DQS
VDDSPD VDD/VDDQ
SPD D0 - D8 D0 - D8
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O 5 I/O 4 I/O 2 I/O 0 I/O 7 I/O 6 I/O 3 I/O 1
D8
VREF VSS
D0 - D8 D0 - D8
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE
PCK PCK
R E G I S T E R
RCS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE
RESET
BA0 -BA1 : SDRAMs DQ0 - D8 A0 -A12 : SDRAMs D0 - D8 RAS : SDRAMs D0 - D8 CAS : SDRAMs D0 - D8 CKE : SDRAMs D0 - D8 WE: SDRAMs D0 - D8
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
1GB, 128M x 72 ECC Module (M312L2923CUS) (Populated as 2 bank of x8 DDR SDRAM Module) Functional Block Diagram
RCS1 RCS0 DQS0 DM0
DM/ CS DQS DM/ CS DQS
DQS4 DM4
DM/ CS DQS DM/ CS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1
I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1
D0
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D9
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5
I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1
D4
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D13
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2
I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1
D1
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6
I/O 7 I/O 4 I/O 2 I/O 0 I/O 6 I/O 5 I/O 3 I/O 1
D5
I/O 0 I/O 3 I/O 5 I/O 7 I/O 1 I/O 2 I/O 4 I/O 6
D14
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
I/O 6 I/O 5 I/O 3 I/O 1 I/O 7 I/O 4 I/O 2 I/O 0
D2
I/O 1 I/O 2 I/O 4 I/O 6 I/O 0 I/O 3 I/O 5 I/O 7
D11
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
I/O 7 I/O 5 I/O 2 I/O 0 I/O 6 I/O 4 I/O 3 I/O 1
D6
I/O 0 I/O 2 I/O 5 I/O 7 I/O 1 I/O 3 I/O 4 I/O 6
D15
t4U.com
DQS3 DM3
DM/ CS DQS DM/ CS DQS
DQS7 .com DM7
DM/ CS DQS DM/ CS DQS
DataShee
D7
I/O 1 I/O 3 I/O 5 I/O 7 I/O 0 I/O 2 I/O 4 I/O 6
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8
I/O 7 I/O 5 I/O 2 I/O 1 I/O 6 I/O 4 I/O 3 I/O 0
D3
I/O 0 I/O 2 I/O 5 I/O 6 I/O 1 I/O 3 I/O 4 I/O 7
D12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 6 I/O 4 I/O 2 I/O 0 I/O 7 I/O 5 I/O 3 I/O 1
D16
DM/
CS
DQS
DM/
CS
DQS
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O 5 I/O 4 I/O 2 I/O 0 I/O 7 I/O 6 I/O 3 I/O 1
D8
I/O 2 I/O 3 I/O 5 I/O 7 I/O 0 I/O 1 I/O 4 I/O 6
D17
Serial PD SCL WP A0 SA0 A1 SA1 A2 SDA
VDDSPD VDD/VDDQ
SPD D0 - D17 D0 - D17
VREF
D0 - D17 D0 - D17
SA2
VSS
CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1
WE PCK PCK
R E G I S T E R
RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE
RESET
BA0 -BA1 : SDRAMs DQ0 - D17 A0 -A12 : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS : SDRAMs DQ0 - D17 CKE : SDRAMs D0 - D8 CKE : SDRAMs D9 - D17 WE: SDRAMs D0 - D17
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
1GB, 128M x 72 ECC Module (M312L2920CUS) (Populated as 1 bank of x4 DDR SDRAM Module) Functional Block Diagram
VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS9 (DM0) DQ4 DQ5 DQ6 DQ7 DQS10 (DM1) DQ12 DQ13 DQ14 DQ15 DQS11 (DM2) DQ20 DQ21 DQ22 DQ23 DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 DQS13 (DM4) DQ36 DQ37 DQ38 DQ39 DQS14 (DM5) DQ44 DQ45 DQ46 DQ47
D0
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D9
D1
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D10
D2
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D11
D3
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D12
D4
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D13
t4U.com
D5
.com
DQS15 (DM6) DQ52 DQ53 DQ54 DQ55 DQS16 (DM7) DQ60 DQ61 DQ62 DQ63 DQS17 (DM8) CB4 CB5 CB6 CB7 DQS I/O 0 I/O 1 I/O 2 I/O 3
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D14
DataShee
DM
CS
Serial PD SCL WP A0 A1 SA1 A2 SA2 SDA
D6
D15
D7
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
SA0 VDDSPD VDD/VDDQ
D16 SPD D0 - D17 D0 - D17 D17 VREF VSS D0 - D17 D0 - D17 Strap: see Note 4
D8
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
S0
BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK
R E G I S T E R
RS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE RESET BA0 -BA1 : SDRAMs DQ0 - D17 A0 -A12 : SDRAMs D0 - D17 RAS : SDRAMs D0 - D17 CAS : SDRAMs DQ0 - D17 CKE : SDRAMs D0 - D17 WE: SDRAMs D0 - D17
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
2GB, 256M x 72 ECC Module [ M312L5628CU0 ] (Populated as 2 bank of x4 DDR SDRAM Module) Functional Block Diagram
VSS RCS1 RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM CB4 CB5 CB6 CB7 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ60 DQ61 DQ62 DQ63 DM8/DQS17 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ44 DQ45 DQ46 DQ47 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ36 DQ37 DQ38 DQ39 DM5/DQS14 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ28 DQ29 DQ30 DQ31 DM4/DQS13 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ20 DQ21 DQ22 DQ23 DM3/DQS12 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ12 DQ13 DQ14 DQ15 DM2/DQS11 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQ4 DQ5 DQ6 DQ7 DM1/DQS10 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DM0/DQS9 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM
D0
D18
D9
D27
D1
D19
D10
D28
D2
D20
D11
D29
D3
D21
D12
D30
D4
D22
D13
D31
D5
D23
D14
D32
t4U.com
.com
DM6/DQS15 DM
DataShee
CS DM
D6
D24
DQ52 DQ53 DQ54 DQ55 DM7/DQS16
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D15
DQS I/O 0 I/O 1 I/O 2 I/O 3
D33
D7
D25
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D16
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D34
D8
D26
D17
D35
VDDSPD Serial PD SCL WP A0
CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1
WE PCK PCK
SPD D0 - D35 D0 - D35
VDD/VDDQ SDA
A1 SA1
A2 SA2
VREF VSS
D0 - D35 D0 - D35
CK0,CK0 PLL
R E G I S T E R
RCS0 RCS1
RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE
SA0
BA0-BAn: SDRAMs D0 - D35 A0-An: SDRAMs D0 - D35 RAS: SDRAMs D0 - D35 CAS: SDRAMs D0 - D35 CKE: SDRAMs D0 - D17 CKE: SDRAMs D18 - D35 WE: SDRAMs D0 - D35
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RESET
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
512MB, 64M x 72 ECC Module (M312L6523CZ0) (Populated as 1 bank of x8 DDR SDRAM Module) Functional Block Diagram
RCS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DM I/O 0 I/O 2 I/O 4 I/O 7 I/O 3 I/O 1 I/O 6 I/O 5 CS DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS DM I/O 0 I/O 2 I/O 4 I/O 7 I/O 3 I/O 1 I/O 6 I/O 5 CS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS DQS4 DM4 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS
D0
D4
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2
D1
D5
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
D2
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7 .com DQS7
D6
t4U.com
DQS3 DM3 DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS
DataShee
DM I/O 0 I/O 2 I/O 4 I/O 7 I/O 3 I/O 1 I/O 6 I/O 5 CS DQS
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
D3
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
D7
VDDSPD
DM I/O 7 I/O 5 I/O 3 I/O 0 I/O 4 I/O 6 I/O 1 I/O 2 CS DQS
SPD DDR SDRAMs D0 - D8
VDD/VDDQ
D8 VREF VSS DDR SDRAMs D0 - D8 DDR SDRAMs D0 - D8 Serial PD
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
SCL WP A0 A1 SA1 A2 SA2 SDA
CS0 BA0-BA1 A0-A12 RAS CAS CKE0 WE
PCK PCK
R E G I S T E R
RCS0 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RWE
RESET
SA0
BA0 -BA1 : DDR SDRAMs D0 - D8 A0 -A12 : DDR SDRAMs D0 - D8 RAS : DDR SDRAMs D0 - D8 CAS : DDR SDRAMs D0 - D8 CKE : DDR SDRAMs D0 - D8 WE: DDR SDRAMs D0 - D8
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
1GB, 128M x 72 ECC Module (M312L2923CZ0) (Populated as 2 bank of x8 DDR SDRAM Module) Functional Block Diagram
RCS1 RCS0 DQS0 DM0
DM/ CS DQS DM/ CS DQS
DQS4 DM4
DM/ CS DQS DM/ CS DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D0
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D9
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D4
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D13
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D1
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D10
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D5
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D14
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DM/
CS
DQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D2
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D11
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D6
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D15
t4U.com
DQS3 DM3
DM/ CS DQS DM/ CS DQS
DQS7 .com DM7
DM/ CS DQS DM/ CS DQS
DataShee
D7
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D3
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D12
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D16
DM/
CS
DQS
DM/
CS
DQS
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
I/O 1 I/O 0 I/O 7 I/O 6 I/O 2 I/O 3 I/O 4 I/O 5
D8
I/O 6 I/O 7 I/O 0 I/O 1 I/O 5 I/O 4 I/O 3 I/O 2
D17
Serial PD SCL WP A0 SA0 A1 SA1 A2 SDA
VDDSPD VDD/VDDQ
SPD D0 - D17 D0 - D17
VREF
D0 - D17 D0 - D17
SA2
VSS
CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1
WE PCK PCK
R E G I S T E R
RCS0 RCS1 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE
RESET
BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 : DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE: DDR SDRAM D0 - D17
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
1GB, 128M x 72 ECC Module (M312L2920CZ0) (Populated as 1 bank of x4 DDR SDRAM Module) Functional Block Diagram
VSS RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB0 CB1 CB2 CB3 DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS I/O 3 I/O 2 I/O 1 I/O 0 CS DM DQS9 (DM0) DQ4 DQ5 DQ6 DQ7 DQS10 (DM1) DQ12 DQ13 DQ14 DQ15 DQS11 (DM2) DQ20 DQ21 DQ22 DQ23 DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 DQS13 (DM4) DQ36 DQ37 DQ38 DQ39 DQS14 (DM5) DQ44 DQ45 DQ46 DQ47
D0
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D9
D1
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D10
CS
DM
D2
D11
CS
DM
D3
D12
CS
DM
D4
D13
t4U.com
D5
.com
DQS15 (DM6) DQ52 DQ53 DQ54 DQ55 DQS16 (DM7) DQ60 DQ61 DQ62 DQ63 DQS17 (DM8) CB4 CB5 CB6 CB7 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
DM
D14
DataShee
DM
CS
Serial PD SCL WP A0 A1 SA1 A2 SA2 SDA
D6
D15
CS
DM
SA0 VDDSPD VDD/VDDQ
D7
D16 SPD D0 - D17 D0 - D17 D17 VREF VSS D0 - D17 D0 - D17
CS
DM
D8
CS0
RCS0_1
R E G I S T E R
RCS0_2 RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0A RCKE0B RWE RESET BA0 -BA1 : DDR SDRAM DQ0 - D17 A0 -A12 :DDR SDRAM D0 - D17 RAS : DDR SDRAM D0 - D17 CAS : DDR SDRAM DQ0 - D17 CKE : DDR SDRAM D0 - D8 CKE : DDR SDRAM D9 - D17 WE:DDR SDRAM D0 - D17
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
BA0-BA1 A0-A12 RAS CAS CKE0 WE PCK PCK
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM resistors: 22 Ohms.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
2GB, 256M x 72 ECC Module [M312L5720CZ0] (Populated as 2 bank of x4 DDR SDRAM Module) Functional Block Diagram
VSS RCS1 RCS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 DQS6 DQ48 DQ49 DQ50 DQ51 DQS7 DQ56 DQ57 DQ58 DQ59 DQS8 CB0 CB1 CB2 CB3 DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS I/O 0 I/O 1 I/O 2 I/O 3 CS DM DQS9 (DM0) DQ4 DQ5 DQ6 DQ7 DQS10 (DM1) DQ12 DQ13 DQ14 DQ15 DQS11 (DM2) DQ20 DQ21 DQ22 DQ23 DQS12 (DM3) DQ28 DQ29 DQ30 DQ31 DQS13 (DM4) DQ36 DQ37 DQ38 DQ39 DQS14 (DM5) DQ44 DQ45 DQ46 DQ47 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 DM DQS I/O 3 I/O 2 I/O 1 I/O 0 DM
CS
CS
D0
D18
D9
D27
CS
DM
D1
D19
D10
DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D28
D2
D20
DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D11
DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D29
CS
DM
D3
D21
D12
DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D30
D4
D22
DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D13
DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D31
CS
DM
D5
D23
D14
t4U.com
.com DQS15
DM (DM6)
DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D32
DataShee
CS DM
CS
DM
D6
D24
DQS16 (DM7)
DQ52 DQ53 DQ54 DQ55
D15
DQS I/O 3 I/O 2 I/O 1 I/O 0
D33
D7
D25
DQS17 (DM8)
DQ60 DQ61 DQ62 DQ63
DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D16
DQS I/O 3 I/O 2 I/O 1 I/O 0 DQS I/O 3 I/O 2 I/O 1 I/O 0
CS
DM
D34
CS
DM
CS
DM
D8
D26
CB4 CB5 CB6 CB7
D17
D35
Serial PD SCL WP A0 SA0
CS0 CS1 BA0-BA1 A0-A12 RAS CAS CKE0 CKE1
WE PCK PCK
VDDSPD VDD/VDDQ SDA A2 SA2
SPD D0 - D35 D0 - D35
A1 SA1
VREF VSS
D0 - D35 D0 - D35
R E G I S T E R
RCS0 RCS1
RBA0 - RBA1 RA0 - RA12 RRAS RCAS RCKE0 RCKE1 RWE RAS: BA0-BA1: DDR SDRAM D0 - D35 A0-A12: DDR SDRAM D0 - D35
PLL* CK0,CK0 * Wire per Clock Loading table/wiring Diagrams
DDR SDRAM D0 - D35
CAS: DDR SDRAM D0 - D35 CKE: DDR SDRAM D0 - D17 CKE: WE:
DDR SDRAM D18 - D35 DDR SDRAM D0 - D35
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
RESET
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Absolute Maximum Ratings
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD,VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1.5 * # of component 50
Preliminary DDR SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Power & DC Operating Conditions (SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Reference voltage I/O Termination voltage(system)
Symbol
VDD VDD VDDQ VDDQ VREF VTT VIH(DC) .com VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH IOL
Min
2.3 2.5 2.3 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5
Unit
V V V V V V V V V V uA uA mA mA mA mA
Note
1 2
t4U.com
Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current
DataShee
3 4
Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM IDD spec table
M312L6523CUS [ (64M x 8) * 9 , 512MB Module ]
Preliminary DDR SDRAM
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 1,700 1,970 420 1,020 600 650 1,160 2,010 2,100 2,600 420 410 3,990 A2(DDR266@CL=2) 1,360 1,630 350 770 530 570 910 1,630 1,670 2,260 350 330 3,430 B0(DDR266@CL=2.5) 1,360 1,630 350 770 530 570 910 1,630 1,670 2,260 350 330 3,430 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M312L2923CUS [ (64M x 8) * 18 , 1GB Module ]
t4U.com
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 2,230 2,500 590 1,420 950 1,040 1,690 2,540 2,630 3,130 590 560 4,520
.com
2,010 2,280 540 1,290 900 990 1,560 2,280 2,330 2,910 540 510 4,080
(VDD=2.7V, T = 10C) B0(DDR266@CL=2.5) 2,010 2,280 540 1,290 900 990 1,560 2,280 2,330 2,910 540 510 4,080 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
A2(DDR266@CL=2)
DataShee
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM IDD spec table
M312L2920CUS [ (128M x 4) * 18 , 1GB Module ]
Preliminary DDR SDRAM
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 2,640 3,180 470 1,290 830 920 1,560 3,270 3,450 4,440 470 430 7,230 A2(DDR266@CL=2) 2,340 2,880 420 1,170 780 870 1,440 2,880 2,970 4,140 420 380 6,480 B0(DDR266@CL=2.5) 2,340 2,880 420 1,170 780 870 1,440 2,880 2,970 4,140 420 380 6,480 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M312L5628CU0 [ (st.256M x 4) * 18 , 2GB Module ]
t4U.com
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A B3(DDR333@CL=2.5) 3,700 4,240 810 2,080 1,530 1,710 2,620 4,330 4,510 5,500 810 735 8,290
.com
A2(DDR266@CL=2) 3,400 3,940 760 1,960 1,480 1,660 2,500 3,940 4,030 5,200 760 685 7,540 B0(DDR266@CL=2.5) 3,400 3,940 760 1,960 1,480 1,660 2,500 3,940 4,030 5,200 760 685 7,540
(VDD=2.7V, T = 10C) Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
DataShee
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM IDD spec table
M312L6523CZ0 [ (64M x 8) * 9 , 512MB Module ]
Preliminary DDR SDRAM
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC (DDR400@CL=3) 1,830 2,100 420 1,020 600 780 1,290 2,150 2,330 2,730 420 410 4,220 B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit 1,700 1,970 420 1,020 600 650 1,160 2,010 2,100 2,600 420 410 3,990 1,360 1,630 350 770 530 570 910 1,630 1,670 2,260 350 330 3,430 1,360 1,630 350 770 530 570 910 1,630 1,670 2,260 350 330 3,430 mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M312L2923BG0 [ (64M x 8) * 18 , 1GB Module ]
t4U.com
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC (DDR400@CL=3) 2,500 2,770 590 1,420 950 1,310 1,960 2,810 2,990 3,400 590 560 4,880
.com
2,230 2,500 590 1,420 950 1,040 1,690 2,540 2,630 3,130 590 560 4,520 2,010 2,280 540 1,290 900 990 1,560 2,280 2,330 2,910 540 510 4,080 2,010 2,280 540 1,290 900 990 1,560 2,280 2,330 2,910 540 510 4,080
(VDD=2.7V, T = 10C) Notes mA mA mA mA mA mA mA mA mA mA mA mA mA Optional
DataShee
B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
DDR SDRAM IDD spec table
M312L2920BG0 [ (128M x 4) * 18 , 1GB Module ]
Preliminary DDR SDRAM
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC (DDR400@CL=3) 2,910 3,450 470 1,290 830 1,190 1,830 3,540 3,900 4,710 470 430 7,680 B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit 2,640 3,180 470 1,290 830 920 1,560 3,270 3,450 4,440 470 430 7,230 2,340 2,880 420 1,170 780 870 1,440 2,880 2,970 4,140 420 380 6,480 2,340 2,880 420 1,170 780 870 1,440 2,880 2,970 4,140 420 380 6,480 mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
M312L5720BG0 [ (128M x 4) * 36, 2GB Module ]
t4U.com
Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC (DDR400@CL=3) 4,240 4,780 810 2,080 1,530 2,250 3,160 4,870 5,230 6,040 810 740 9,010
.com
3,700 4,240 810 2,080 1,530 1,710 2,620 4,330 4,510 5,500 810 740 8,290 3,400 3,940 760 1,960 1,480 1,660 2,500 3,940 4,030 5,200 760 690 7,540 3,400 3,940 760 1,960 1,480 1,660 2,500 3,940 4,030 5,200 760 690 7,540
(VDD=2.7V, T = 10C) Notes mA mA mA mA mA mA mA mA mA mA mA mA mA Optional
DataShee
B3 (DDR333@CL=2.5) A2 (DDR266@CL=2) B0 (DDR266@CL=2.5) Unit
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 Max
Preliminary DDR SDRAM
Unit V V V V
Note
1 2
0.5*VDDQ+0.2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
t4U.com
Input/Output Capacitance
Parameter
.com
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2 Min 9 9 9 11 10 10 10
(TA= 25C, f=100MHz) Unit pF pF pF pF pF pF pF
DataShee
M312L6523CUS,M312L2920CUS M312L2923CUS,M312L5720CU0 Max 11 11 11 12 11 11 11 Min 9 9 9 11 14 14 14 Max 11 11 11 12 16 16 16
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK0 ) Input capacitance(DM0~DM8) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7)
Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0) Input capacitance( CS0) Input capacitance( CLK0, CLK0 ) Input capacitance(DM0~DM8) Data & DQS input/output capacitance(DQ0~DQ63) Data input/output capacitance (CB0~CB7)
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Cout2
M312L6523CZ0,M312L2920CZ0 Min 9 9 9 11 10 10 10 Max 11 11 11 12 11 11 11
M312L2923CZ0,M312L5720CZ0 Min 9 9 9 11 13 13 13 Max 11 11 11 12 15 15 15
Unit pF pF pF pF pF pF pF
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge CL=2.0 CL=2.5 CL=3.0 tCH tCL tDQSCK tAC tDQSQ
Preliminary DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCK
CC B3 A2 B0 (DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5) Unit Min Max Min Max Min Max Min Max
55 70 40 15 15 10 15 2 6 5 0.45 0.45 -0.55 -0.65 12 10 0.55 0.55 +0.55 +0.65 0.4 70K 60 72 42 18 18 12 15 1 7.5 6 0.45 0.45 -0.6 -0.7 12 12 0.55 0.55 +0.6 +0.7 0.45 70K 65 75 45 20 20 15 15 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 +0.7 +0.7 1.0 -0.75 15 0.5 0.5 2.2 1.75 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) 0.55 0.6 tHP -tQHS tCLmin or tCHmin 0.4 20 (tWR/tCK) + (tRP/tCK) 7.8 0.75 0.6 tHP -tQHS tCLmin or tCHmin 0.4 20 (tWR/tCK) + (tRP/tCK) tCK +0.75 +0.75 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K 65 75 45 20 20 15 15 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 1.0 -0.75 15 0.5 0.5 2.2 1.75 75 200 7.8 0.75 0.6 +0.75 +0.75 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 120K ns ns ns ns ns ns ns tCK ns ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK us ns ns ns tCK
Note
22
t4U.com
Read Preamble tRPRE Read Postamble tRPST CK to valid DQS-in tDQSS DQS-in setup time tWPRES DQS-in hold time tWPRE DQS falling edge to CK rising-setup time tDSS DQS falling edge from CK rising-hold time tDSH DQS-in high level width tDQSH DQS-in low level width tDQSL Address and Control Input setup time(fast) tIS Address and Control Input hold time(fast) Address and Control Input setup Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time tIH tIS tIH tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL
0.9 1.1 0.9 1.1 0.4 0.6 0.4 0.6 0.72 1.25 0.75 1.25 0 0 0.25 0.25 0.2 0.2 0.2 0.2 0.35 0.35 0.35 0.35 .com 0.6 0.75 0.6 0.7 0.7 -0.65 10 0.4 0.4 2.2 1.75 75 200 7.8 tHP -tQHS tCLmin or tCHmin 0.4 15 (tWR/tCK) + (tRP/tCK) 0.5 0.6 +0.65 +0.65 0.75 0.8 0.8 -0.7 12 0.45 0.45 2.2 1.75 75 200
13
15, 17~19 15, 17~19
DataShee
16~19 16~19 11 11 j, k j, k 18 18
14 21 20, 21 21 12
23
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
System Characteristics for DDR SDRAM
Preliminary DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 & DDR200 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design.
Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD DDR200 MIN 0.5 MAX 4.0 Units V/ns Notes a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes i i i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes k k k
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps Notes j j
t4U.com
+/- 0.5 V/ns
ps j .com
DataShee
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR266B MIN TBD MAX TBD DDR200 MIN 0.67 MAX 1.5 Notes e,m
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
System Notes : a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
Preliminary DDR SDRAM
Test point Output 50 VSSQ Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
VDDQ 50 Output Test point Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process .com Maximum : 0 C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic.
t4U.com
DataShee
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H H L H CKEn X X H L H X CS L L L L H L RAS L L L H X L
Preliminary DDR SDRAM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) CAS L L L H X H WE BA0,1 A10/AP L L H H X H V A0 ~ A9 A11, A12 Note 1, 2 1, 2 3 3 3 3
OP CODE OP CODE X X Row Address (A0~A9, A11,A12) L H L H X V X L H X X
Column Address Column Address
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
H H H H H L H L H H
X X X X L H
L L L L H L X H
H H H L X V X X
L L H H X V X X H X V X H
H L L L X V X X H X V
V V
4 4 4 4, 6 7 5
Active Power Down
t4U.com
Precharge Power Down Mode
Entry Exit DM No operation (NOP) : Not defined
L .com L H H H L H L X V X X X H
DataShee
X
X X H X
8 9 9
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Physical Dimensions : 64M x 72 (M312L6523CUS)
Preliminary DDR SDRAM
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950) 0.0787 R (2.00)
0.118 Min (3.00 Min)
PLL
A
B
0.100 (2.30)
t4U.com
.com
A
0.393 (10.00)
0.78 (19.80)
2.500 +0.1/-0.0
B
0.10 M CBA 0.157 Max (3.99 Max)
0.7 (17.80)
1.2 +/-0.06 (30.48 +/-0.15)
REG
DataShee
REG
(0.157) (4.00)
0.050 0.0039 (1.270 0.10)
0.100 0.0079
0.250 (6.350)
(2.50 0.2 )
0.039 0.002 (1.000 0.050)
0.118 Min (3.00 Min) 0.0787 R (2.00)
0.1496 (3.80)
0.0078 0.006 (0.20 0.15) 0.050 (1.270) 0.1575 0.004 (4.00 0.1) 0.10 M C A M B
2.175
0.071 (1.80)
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8 DDR SDRAM, TSOPII SDRAM Part No : K4H510838C
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Preliminary DDR SDRAM
Physical Dimensions: 128Mx72 (M312L2923CUS), 128Mx72 (M312L2920CUS)
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950) 0.0787 R (2.00)
0.118 Min (3.00 Min)
PLL
A
B
0.100 (2.30)
t4U.com
.com
A
0.393 (10.00)
0.78 (19.80)
2.500 +0.1/-0.0
B
0.10 M CBA 0.157 Max (3.99 Max)
0.7 (17.80)
1.2 +/-0.06 (30.48 +/-0.15)
REG
DataShee
REG
(0.157) (4.00)
0.050 0.0039 (1.270 0.10)
0.100 0.0079
0.250 (6.350)
(2.50 0.2 )
0.039 0.002 (1.000 0.050)
0.118 Min (3.00 Min) 0.0787 R (2.00)
0.1496 (3.80)
0.0078 0.006 (0.20 0.15) 0.050 (1.270) 0.1575 0.004 (4.00 0.1) 0.10 M C A M B
2.175
0.071 (1.80)
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDRSDRAM, TSOPII SDRAM Part No. : K4H510838C, K4H510438C
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Physical Dimensions: st.256Mx72 (M312L5628CU0)
Preliminary DDR SDRAM
Units : Inches (Millimeters)
5.25 0.005 (133.350 0.13) 5.171 (131.350) 5.077 (128.950) 0.0787 R (2.00)
0.118 Min (3.00 Min)
Reg.
0.7 (17.80) 1.2 +/-0.06 (30.48 +/-0.15) 0.10 M CBA 0.268 Max (6.81 Max)
A
B
0.100 (2.30)
A
B
t4U.com
.com
0.393 (10.00)
0.78 (19.80)
2.500 +0.1/-0.0
DataShee
PLL
(0.157) (4.00)
0.050 0.0039 (1.270 0.10)
0.100 0.0079
0.250 (6.350)
(2.50 0.2 )
0.039 0.002 (1.000 0.050)
0.118 Min (3.00 Min) 0.0787 R (2.00)
0.1496 (3.80)
0.0078 0.006 (0.20 0.15) 0.050 (1.270) 0.1575 0.004 (4.00 0.1) 0.10 M C A M B
2.175
0.071 (1.80)
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is st.256Mx4 SDRAM, 66TSOPII SDRAM Part NO : K4H1G0638C
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Physical Dimensions: 64Mx72 (M312L6523CZ0)
Preliminary DDR SDRAM
Units : Millimeters
133.35 A 128.95 A 2x 3.00 MIN W1 4x 4.00+/-0.1 V1
12.00 1.27 +/-0.1
28.575 +/-0.15 B
19.80 B1
2x DIA. 2.50 +0.1/-0.00 N
1
10.00 B2
a 64.77 P2 120.65 P1 49.53 P3
b
92
6.35
2.99 MAX
93
184
t4U.com
.com
DataShee
6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05
0.20 +/-0.15 T
2.50 G
3.80 W
V
1.80 MAX 0.178 D1 E 1.27
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838C-Z***,
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Physical Dimensions: 128Mx72 (M312L2923CZ0), (M312L2920CZ0)
Preliminary DDR SDRAM
Units : Millimeters
133.35 A 128.95 A 2x 3.00 MIN W1 4x 4.00+/-0.1 V1
12.00 1.27 +/-0.1
28.575 +/-0.15 B
19.80 B1
2x DIA. 2.50 +0.1/-0.00 N
1
10.00 B2
a 64.77 P2 120.65 P1 49.53 P3
b
92
6.35
3.99 MAX
93
184
t4U.com
.com
DataShee
6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05
0.20 +/-0.15 T
2.50 G
3.80 W
V
1.80 MAX 0.178 D1 E 1.27
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx8, 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No. : K4H510838C-Z***, K4H510438C-Z***
Rev. 0.1 October, 2004
.com
www..com
512MB, 1GB, 2GB Registered DIMM
Physical Dimensions: 256Mx72 (M312L5720CZ0)
Preliminary DDR SDRAM
Units : Millimeters
133.35 A 128.95 A 2x 3.00 MIN W1
12.0 1.27 +/-0.1
4x 4.00+/-0.1 V1 19.80 B1
30.48 +/-0.15 B
10.0
10.00 B2
1
2x DIA. 2.50 +0.1/-0.00 N 64.77 P2
a 49.53 P3 120.65 P1
b
92
3.99 MAX
6.35
93
184
t4U.com
.com
6.35 X 2.175 X1 X2 4.175 D 1.0 +/-0.05
0.20 +/-0.15 T 2.50 +/-0.2 G
3.80 W
V
1.80 MAX 0.178 D1 E 1.27
Detail A
Detail B
Tolerances : 0.005(.13) unless otherwise specified The used device is 128Mx4 DDR SDRAM, FBGA DDR SDRAM Part No : K4H510438C-Z***
Rev. 0.1 October, 2004
.com

▲Up To Search▲

Price & Availability of A3-44PA-2SV

	To Download A3-44PA-2SV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .